1. Field of the Invention
The present invention relates to a power on reset circuit and more particularly, to a power on reset circuit capable of obtaining a stable operation regardless of a ramp up time of a power supply voltage or a process variation.
2. Description of the Prior Art
A flash EEPROM generally includes logic circuits, and after a setup of a power supply voltage, the logic circuits should be initialized with a predetermined state. Thus, a power on reset circuit is used to generate a signal capable of initializing the logic circuits as soon as the power supply voltage is set up.
Hereinafter, a conventional power on reset circuit will be described with reference to FIG. 1.
FIG. 1 is a circuit diagram showing a conventional power on reset circuit, and the construction thereof is as follows.
First to third PMOS transistors P1 to P3 are coupled between a power terminal and a second node Q2. The first PMOS transistor P1 is driven according to a potential of a first node Q1, the second PMOS transistor P2 serves as a diode, and the third PMOS transistor P3, whose a gate terminal is coupled to a ground terminal Vss, is maintained at a turned-on state. First to fifth NMOS transistors N1 to N5 are coupled between the second node Q2 and the ground terminal Vss and are always maintained at a turned-on state since their gate terminals are coupled to the power terminal. A sixth NMOS transistor N6 is coupled between the power terminal and the second node Q2, whose a gate terminal is coupled to the second node Q2. Fourth and fifth PMOS transistors P4 and P5 are coupled between the power terminal and a third node Q3. The fourth PMOS transistor P4 is driven according to a potential of the first node Q1, and the fifth PMOS transistor P5, whose a gate terminal is coupled to the ground terminal Vss, is always maintained at a turned-on state. Seventh to ninth NMOS transistors N7 to N9 are coupled between the third node Q3 and the ground terminal Vss, whose gate terminals are coupled to the second node Q2, respectively. Third and fourth capacitors C3 and C4 are coupled in parallel between the power terminal and the third node Q3. Tenth to thirteen NMOS transistors N10 to N13 are coupled between the third node Q3 and the ground terminal Vss, whose gate terminals are coupled to the first node Q1, respectively. A signal of the third node Q3 is delayed through first to sixth inverters I1 to I6 to output a reset signal RST. Meanwhile, a plurality of serially-coupled PMOS transistors and a fourteenth NMOS transistor N14 are coupled between the power terminal and the first node Q1. Each gate terminal of the serially-coupled PMOS transistors is coupled to the ground terminal Vss. A first capacitor C1 is coupled between the first node Q1 and the ground terminal Vss.
Hereinafter, a driving method of the conventional power on reset circuit will be described.
At an initial state, the first node Q1 is maintained at a low state. Therefore, if the power supply voltage Vcc is applied more than a threshold voltage Vpn of a PMOS transistor, the first and fourth PMOS transistors P1 and P4 are turned on. The power supply voltage Vcc is supplied to the second node Q2 through the turned-on first PMOS transistor P1, the second and third PMOS transistors P2 and P3. However, the second node Q2 is maintained at a low state through the first to fifth NMOS transistors N1 to N5, coupled between the second node Q2 and the ground terminal Vss, whose gate terminals are coupled to the power supply terminal. Since the second node Q2 is maintained at a low state, the sixth NMOS transistor N6 is turned on, so that the power supply voltage Vcc is supplied to the second node Q2 through the sixth NMOS transistor N6. The voltage Vcc is discharged to the ground terminal Vss through the second capacitor C2 so that the second node Q2 is dropped to the ground level. Accordingly, the sixth to ninth NMOS transistors N7 to N9 are turned off, wherein the sixth to ninth NMOS transistors N7 to N9 are coupled between the third node Q3 and the ground terminal Vss, whose gate terminals are coupled to the second node Q2. Meanwhile, the power supply voltage Vcc is supplied to the second node Q2 through the turned-on fourth PMOS transistor P4 and the fifth PMOS transistor P5. Since the seventh to ninth PMOS transistors N7 to N9 are turned off, the second node Q2 is maintained at a high state. Since the tenth to thirteenth NMOS transistors N1O to N13 coupled between the third node Q3 and the ground terminal Vss, whose gate terminals is coupled to the third node Q3, are turned off by a potential of the first node Q1 having the low state, the third node Q3 is maintained at a high state. A signal of the third node Q3 maintained at the high state is delayed through the first to sixth inverters I1 to I6 for a predetermined time to output a reset signal RST, thereby resetting a chip.
The gradually-increasing power supply voltage Vcc is delayed due to a plurality of the serially-coupled PMOS transistors and the first capacitor C1 for a predetermined time and supplied to the first node Q1, and a potential of the first node Q1 is increased due to the voltage. The first and the fourth PMOS transistors P1 and P4 are turned off, so that a supply of the power supply voltage is stopped. The tenth to the thirteenth NMOS transistors N1O to N13 are turned off, so that a potential of the third node Q3 becomes a low state. As a result, since a signal of the low state is outputted through the first to sixth inverters I1 to I6, a reset operation is stopped.
FIGS. 2 and 3 shows the output waveforms of FIG. 1 according to a ramp up time. Here, FIG. 2 is an output waveform when the ramp up time is 5 msec, and FIG. 3 is an output waveform when the ramp up time is 200 msec.
As can be seen from FIG. 2, the power up reset circuit such as shown in FIG. 1 generates the reset signal of approximately 2V for 2msec, when the power supply voltage Vcc is applied and increased. As can be seen from FIG. 3, however, the reset voltage is not generated when the ramp up time is 200 msec. That is, in a slow ramping of 200 msec as an optimized parameter, since the reset signal is not generated, the chip can not be reset.